1. Field of the Invention
The present invention relates to failure analysis of a semiconductor device, and more particularly to an analytic structure for failure analysis of a semiconductor device.
2. Description of the Related Art
Generally, in the mass production of a semiconductor device, the securing of a stabilized production technology capable of maintaining a profitable yield is desired. A development procedure of the semiconductor device is a series of procedures including a designing procedure, a procedure for a pilot production, and a procedure of testing the pilot-fabricated products, in order to secure stabilized production technology. Meanwhile, a failure analysis is a series of feedback procedures that are designed to determine the causes for failures in the pilot-fabricated semiconductor devices, and to improve them.
In particular, since methods of designing and fabricating the semiconductor device may be changed according to the result of the failure analysis, an adequate failure analysis is very important in the development procedure of the semiconductor device. Accordingly, an erroneous failure analysis can delay the development period of products by increasing the amount of trial and error needed to reach development. In this point of view, a rapid and accurate failure analysis is very important for securing a short development period and preemption over markets of semiconductor devices.
In general, in order to analyze failures efficiently, test patterns are formed on a semiconductor wafer according to various design rules. Various electrical measurements performed for the test patterns are used for evaluating structural or electrical properties of various microscopic electronic devices. For this reason, the test patterns are designed to monitor the structural/electrical properties of elements constituting the semiconductor device.
Fabrication processes of the semiconductor device can be primarily classified into a front-end process incorporating a plurality of steps carried out until a transistor is formed and a back-end process following formation of the transistor. Herein, the back-end process generally involves formation of interconnect structures that connect the transistors and a process for forming an interlayer dielectric layer which operates to mechanically support and electrically insulate the interconnection structures. U.S. Patent Publication No. 2003-034558 (Eiichi Umemura, et al.) discloses a technology with regard to an inspection pattern having a contact chain structure in order to evaluate the back-end process. In the Umemura, et al. disclosure, although it is possible to recognize that failures with regard to interconnections, e.g., failures of interconnections such as short or open, have occurred, it is impossible to obtain detailed information with regard to types or locations of the failures.
When accurate locations of the failures are determined, a portion of a semiconductor substrate corresponding to those locations can be accurately cut off by using a focused ion beam (FIB) or the like and it is possible to visually enlarge a cut section for failure analysis using a scanning electron microscope (SEM). However, when the accurate locations of the failures are not known, a plurality of wafer cutting processes are required for obtaining enlarged visual information which can be used for failure analysis. That is, provided that the failures exist in the cut section during the wafer cutting process, the failures may be enlarged so that they can be analyzed through the SEM. On the contrary, if there is not accurate information with regard to the locations of the failures, it is not certain whether the locations of the failures exist in the cut section. As a result, it may be necessary to carry out the wafer cutting process many times. In particular, in the case of analyzing the semiconductor device having limited number of failures therein, a wafer specimen may be damaged during an inaccurate wafer cutting process so that it may be impossible to analyze the failures. In this case, since the causes for the failures are not discovered, development time may be further delayed.